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How the PlayStation 3 Shuttles Bits
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Short Description: Exciting, agile game play requires a. fast memory-processor bus. The PS3's. memory (four XDR DRAMs, by Rambus). exchanges data with the Cell processor ..
Content Inside: to Speed up data tranSferS between the Cell processor and its data as short as possible. Despite these improvements, modern memory chips, the PS3's designers adopted a novel memory system CPUs can spend more than half their time--and often much architecture that, Rambus says, addresses some of the limitations of more, Davis notes--just waiting for data to come from memory. current DRAMs. To understand how these limitations came about, The growing gap between processor and memory performance consider first the co-evolution of microprocessors and memory. isn't anything you'd notice while reading e-mail, typing a report, Moore's Law tells us that transistor densities on chips are or listening to music on your PC. But in high-performance doubling every 18 months or so. This evolution has been accom- systems like servers or demanding applications like three- panied by a doubling, on a similar time scale, in the clock rates of dimensional games, this bottleneck becomes the system's main processor chips, basically because smaller transistors can toggle performance limiter. To tackle the problem, one key design shift on and off faster. But memory clock rates, which serve as an has been to integrate the memory controller into the processor. indicator of memory data-transfer rates, are doubling much more In most PCs today, processor and memory communicate via an slowly--about every 10 years. The result is that memory can't intermediate chip--the memory controller--an additional step fetch data to the processor fast enough, a bandwidth bottleneck that adds latency. The PS3 has its memory controller in the Cell. that has increasingly constricted over the past few decades. (AMD's Opteron was one of the first general-purpose processors The bandwidth gap is just part of the problem. The other part to include an on-die memory controller.) The integration can cut is related to latency, the time it takes the memory to produce a memory latency roughly in half, and it lets the processor take chunk of data requested by the processor. This delay can vary advantage of the memory's full speed. from tens to hundreds of nanoseconds. That may not seem like But achieving any further reductions in latency would be difficult, much, but in a mere 50 nanoseconds a 3.8-GHz processor can go requiring redesigns of the DRAM's bit-storage and bit-retrieving through 190 clock cycles. "You don't want the processor waiting mechanisms. So engineers are instead concentrating on maximiz- for that long," says Brian T. Davis, a professor of electrical and ing memory bandwidth. "The way that the memory interfaces have computer engineering at the Michigan Technological University, changed, it really has been about bursting wider and wider chunks in Houghton. The latency problem prompted chip makers years of data across a channel," says Graham Allan, a director of market- ago to embed some DRAM caches directly onto CPU chips, as ing at Mosaid Technologies Inc., in Kanata, Ont., Canada, which well as to concoct some processing tricks to keep the wait for develops memory controllers and chip-to-chip interfaces. How the PlayStation 3 Shuttles Bits Superfast chip-to-chip connections DIFFERENTIAL SIGNALING will keep the pS3's processor, memory, Differential signaling uses two parallel and graphics processor always copper traces to send one bit. To repre- busily crunching data. 1.0 v sent a 1, one trace is driven to 1.0 volt while the other is driven to 1.2 V. To represent a 0, the voltages are reversed. 1.2 v The main advantage is immunity to memory interference: spurious noise affects adjacent traces similarly, and so the volt- age difference between them is maintained. 8-byte-wide bus 3.2 ghz PROCESSOR-GRAPHICS CHIP CONNECTION 25.6 gB/s Stunning graphics require fast communication between the processor and the graphics processor. processor The PS3's Cell processor sends data to the RSX MEMORY-PROCESSOR graphics chip, by Nvidia, at 20 GB/s and it receives CONNECTION data back at 15 GB/s--or five to 10 times what you Exciting, agile game play requires a can get with today's best PC-bus technology. fast memory-processor bus. The PS3's memory (four XDR DRAMs, by Rambus) exchanges data with the Cell processor at 25.6 gigabytes per second--or double 4-byte-wide bus what a high-end PC can deliver. 5 ghz 3-byte-wide bus 5 ghz PROGRAMMABLE DELAYS High-speed signals travel- graphics processor ing along different copper traces may not arrive at the same time, causing errors. B r In the PS3, time-control y A N circuitry precisely delays c h r signals on certain traces, i S t so that all signals show up i e d together at the receiver. e S i g N www.spectrum.ieee.org August 2006 | ieee Spectrum | NA 37
